1. Technical Field
The present invention relates in general to a system and method for improved branch performance in pipelined computer architectures. More particularly, the present invention relates to a system and method for instructing a pipeline as to which instruction to execute from a plurality of executable instructions.
2. Description of the Related Art
Code execution performance is an integral factor of a computer system. An increase in code execution performance increases the overall performance of a computer system. Pipelining is used in a computer system to improve code execution performance of a computer system. Pipelining is a technique whereby a microprocessor begins executing a second instruction before the microprocessor finishes a first instruction Several instructions are simultaneously in a pipeline, each at a different processing “stage”.
A pipeline is divided into stages and each stage executes its operation concurrently with the other stages. For example, a pipeline may be divided into an instruction decode stage and an instruction execution stage. When a stage completes an operation, the stage passes its result to a following stage in the pipeline and fetches a subsequent operation from a preceding stage in the pipeline. The results of each instruction emerge at the end of a pipeline in rapid succession.
Pipelining does not decrease the time for individual instruction execution but rather it increases instruction throughput. The throughput of the instruction pipeline is determined by how often an instruction exits in the pipeline. A challenge found, however, is that a pipeline often encounters a “stall” which prevents the pipeline from executing a particular instruction during a designated clock cycle. For example, a stall occurs when an instruction cannot execute because the instruction uses a particular register's value whereby the register is currently in use by a previous instruction. A pipeline stall creates a situation at subsequent clock cycles whereby the pipeline is faced with a plurality of instructions to execute that require the same resources and the pipeline has to select one instruction to execute from the plurality of executable instructions. In this situation, the pipeline executes instructions in sequential order.
Branch instructions are used in code which branch to a particular code segment based upon the results of a condition, such as the value of a register. When a branch instruction encounters a stall while in a pipeline, the pipeline continues to load instructions subsequent to the branch instruction that may be cleared depending upon the result of the branch instruction. A challenge found is identifying an instruction from a plurality of executable instructions, which minimize branch instruction stall occurrences.
What is needed, therefore, is a system and method for identifying and executing an instruction from a plurality of executable instructions, which minimize branch instruction stall occurrences, thereby improving branch performance in a pipeline.